The typical semiconductor memory includes an array of memory cells organized in intersecting rows and columns. The cells along each row in the array are coupled to a conductive wordline whose voltage is controlled by an associated row decoder. The cells of each column are coupled to at least one bitline, which is in turn coupled to and controlled by a sense amplifier and a column decoder. During an access, a row address is presented to the row decoder to activate (select) the cells of a corresponding row in the array. Data is then exchanged (read or written) with a location, comprising one or more cells along the selected row, through the corresponding sense amplifier(s) and the column decoder in response to a column address.
In the case of a dynamic random access memory (DRAMs), memory operations, including accesses, are timed by a master clock CLK, (synchronized), a row address strobe (/RAS) and a column address strobe (/CAS). Two periods, an active cycle and a precharge cycle, together constitute one random cycle. First, /RAS and /CAS allow for the word-serial input of row and column addresses from a multiplexed address bus. Second, /RAS times the active and precharge cycles. When /RAS is in a logic high state, the DRAM device is in a precharge, during which the nodes of various dynamic circuits, such as those used in the column and row decoders, are brought to a predetermined voltage. Most importantly, during the precharge cycle the bitlines of the cell array are voltage equalized. Then, with the falling edge of /RAS, the device enters the active state and the row address presented to the address pins is latched into the address latches. After a very small delay for set up, the column address is presented at the address pins and latched-in to the address latches with /CAS. A short time thereafter the addressed cells (location) can be accessed (i.e. a "random access" can be performed). During page mode accesses, additional column addresses are input with additional falling edges of /CAS (i.e. /CAS cycling) to access a series of locations or "pages" along the selected row. At the end of the active state, /RAS returns to a logic high state and the device re-enters precharge.
Similar accessing schemes are used in other types of volatile memories, such as static random access memories (SRAMs), as well as non-volatile memories, such as electrically-programmable read-only memories (EPROMs). The only significant differences between the access operations of these devices and the DRAM discussed above is in the actual circuit construction. For example, while DRAMs are normally constructed from dynamic circuitry and operate in the precharge and active states described above in order to save power, SRAMs are typically designed for speed and are therefore normally constructed from static circuitry and operate in a single active cycle.
In each type of conventional semiconductor memory however, the row and column decoders are hardwired such that a given row or column address always selects only one corresponding row or column in the array. Conversely, a given row or column in the array must always be selected using the same row or column address. Thus, because the address decoders are hardwired, an address selecting a given row/column of cells cannot be "moved" and used to address another row/column of cells. Only means by which data can be moved from one location to another is by changing the address as required to access that data at the new location.
The hardwired address decoders of presently available memory devices create substantial disadvantages in many memory applications, such as the construction and operation of the main memory subsystem of information processing systems. In particular, fixed address memories are inefficient when used in the system (main) memory of PC systems running the popular operating systems and applications software. In these systems, each of the memory devices normally has the identical address space which makes individual chip accessing difficult, in light of limitations on the CPU and software operations, when a small amount of main memory is repeatedly and continually required.
Most often, the operating system, in conjunction with the CPU and application software, generates addresses to access (read from or write to) memory as is most convenient to execute a given task. In view of the relative inexpensiveness of memory, efficient use of memory becomes a secondary consideration next to system operating performance. In fact, typically, execution of a given instruction always associates a given piece of data, such as an operand called for by that instruction, with a particular address to memory. Thus, during the execution of the instructions required for a given task, the operating system and CPU may generate addresses which, because of the fixed nature of the address decoding within the memory devices of the system memory, results in data being accessed to locations distributed across multiple chips. This distribution of data throughout the system memory takes place, even though the type of task being performed and/or the type of data being operated on suggests that the required accesses would be more efficient if made to fewer chips, if not a single chip. Further, even when the addresses are to the same chip, the majority of the time the resulting accesses are not to the same page, and as a result multiple random accesses are still required rather than more efficient page accesses.
In sum, in currently available PC systems, memory efficiency is at the mercy of the CPU and the operating system in light of the fixed addressing of conventional memory devices. Among other things, the fixed addressing scheme of presently available memory devices prevents accesses to non-contiguous memory spaces to be redirected to a contiguous memory space. In particular, no means are available for redirecting addresses such that data required for a given operation or task can be accessed from a single chip, let alone a single page in a single chip.
Thus, the need has arisen for memory devices with programmable decoders and systems and methods using the same. Such memories, systems and methods should allow memory accesses to be optimized and unused memory space minimized.